Verilator
/All repositories
Overview
HEALTH SCORE
Excellent
94out of 100
Strong maintainer coverage and development cadence. Security posture is the only remaining gap.
LIFECYCLE
Active
Consistent commits, responsive maintainers, regular releases, and healthy issue triage.
Health breakdown
Excellent(94/100)
Maintainer availability, known risks and supply chain posture, and whether the project is actively developed or appropriately stable.
Maintainer responsiveness
Median response time is 0 days.
Bus factor
23 active maintainers currently have merge rights.
Organization Diversity
Contributors span 207 organizations.
Project Achievements
Leaderboards
About
Verilator is an open-source tool that converts Verilog and SystemVerilog hardware description language (HDL) code into C++ or SystemC for simulation and verification. It performs lint checks, generates executable models, and is widely used in digital design and hardware verification workflows.
First commit
Software value
$22M
Tags
compilers
cpp
rtl
system-verilog
systemc
verilator
verilog
verilog-simulator
License(s)
Other
Data sources
Git
GitHub