Clash
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Overview
HEALTH SCORE
Healthy
81out of 100
Solid maintainer coverage and development cadence. Security posture keeps the score from reaching Excellent.
LIFECYCLE
Active
Consistent commits, responsive maintainers, regular releases, and healthy issue triage.
Health breakdown
Healthy(81/100)
Maintainer availability, known risks and supply chain posture, and whether the project is actively developed or appropriately stable.
Maintainer responsiveness
Median response time is 8 days.
Bus factor
13 active maintainers currently have merge rights.
Organization Diversity
Contributors span 27 organizations.
Project Achievements
Leaderboards
About
Clash is a functional hardware description language that borrows concepts from Haskell. It enables the design and verification of digital circuits through high-level functional programming abstractions, allowing developers to write type-safe hardware descriptions that can be automatically translated to VHDL, Verilog, or SystemVerilog.
First commit
Software value
$4.8M
Tags
asic
fpga
hardware-description-language
haskell
systemverilog
verilog
vhdl
License(s)
Other
Data sources
Git
GitHub