Chisel
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Overview
HEALTH SCORE
Fair
65out of 100
Development cadence drags the score down. Security posture and maintainer coverage help keep it from falling further.
LIFECYCLE
Active
Consistent commits, responsive maintainers, regular releases, and healthy issue triage.
Health breakdown
Fair(65/100)
Maintainer availability, known risks and supply chain posture, and whether the project is actively developed or appropriately stable.
Maintainer responsiveness
Median response time is 0 days.
Bus factor
17 active maintainers currently have merge rights.
Organization Diversity
Contributors span 101 organizations.
Project Achievements
Leaderboards
About
The Constructing Hardware in a Scala Embedded Language (Chisel) is an open-source hardware description language (HDL) used to describe digital electronics and circuits at the register-transfer level that facilitates advanced circuit generation and design reuse for both ASIC and FPGA digital logic designs.
First commit
Software value
$4.7M
Maturity
Graduated
Tags
chisel
chisel3
scala
firrtl
rtl
chip-generator
verilog
License(s)
Apache-2.0
Unlicense
Other
Data sources
Git
GitHub