6 projects
Verilator
Verilator is an open-source tool that converts Verilog and SystemVerilog hardware description language (HDL) code into C++ or SystemC for simulation and verification. It performs lint checks, generates executable models, and is widely used in digital design and hardware verification workflows.
Contributors
1,398
Organizations
231
Software value
$19M
GHDL
VHDL 2008/93/87 simulator
Contributors
944
Organizations
176
Software value
$39M
Icarus Verilog
Icarus Verilog
Contributors
630
Organizations
148
Software value
$12M
CORE-V Verification
Functional verification project for the CORE-V family of RISC-V cores.
Contributors
339
Organizations
52
Software value
$23M
CoHDI
CoHDI (Compiler for Hardware Description and Implementation) is a project focused on hardware description and implementation, likely involving compiler technology for hardware design.
Contributors
24
Organizations
9
Software value
$1.1M
Verible
Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server
This project hasn't been onboarded to LFX Insights.