19 projects
LLVM AIE
Fork of LLVM to support AMD AIEngine processors
Contributors
7,857
Organizations
568
Software value
$769M
Yosys Open SYnthesis Suite
Yosys is an open-source framework for RTL synthesis and formal verification of digital circuits. It takes input in HDL formats like Verilog and VHDL, performs synthesis and optimization of digital logic, and can output to various formats for FPGA implementation or ASIC design flows.
Contributors
1,164
Organizations
315
Software value
$14M
OpenROAD
OpenROAD is an integrated chip physical design tool that performs RTL-to-GDS implementation of digital circuits. It provides automated placement and routing capabilities for electronic design automation (EDA), aiming to produce manufacturable layouts from RTL specifications with minimal human intervention.
Contributors
854
Organizations
101
Software value
$457M
CVA6 RISC-V CPU
The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
Contributors
851
Organizations
110
Software value
$19M
Chipyard
An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
Contributors
659
Organizations
96
Software value
$1.6M
CIRCT
CIRCT (Circuit IR Compilers and Tools) is a framework for building circuit design tools and compilers, extending LLVM's infrastructure to support hardware design and synthesis. It provides intermediate representations and compiler tools for describing and manipulating circuits at various levels of abstraction.
Contributors
538
Organizations
124
Software value
$9M
CHIPS Alliance Projects
The CHIPS Alliance develops high-quality, open source hardware designs relevant to silicon devices and FPGAs.
Contributors
399
Organizations
65
Software value
$2.1M
Verilog to Routing
Verilog-to-Routing (VTR) is an open-source CAD tool designed for FPGA architecture and CAD research. It provides a complete flow from Verilog HDL to FPGA routing, including synthesis, packing, placement, and routing for FPGA architectures.
Contributors
217
Organizations
60
Software value
$217M
Apio
:seedling: Open source ecosystem for open FPGA boards
This project hasn't been onboarded to LFX Insights.
CORE-V Wally
CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, M and Q extensions, and optional caches, BP, FPU, VM/MMU, AHB, RAMs, and peripherals.
This project hasn't been onboarded to LFX Insights.
Clash Compiler
Haskell to VHDL/Verilog/SystemVerilog compiler
This project hasn't been onboarded to LFX Insights.
Ibex
Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
This project hasn't been onboarded to LFX Insights.
NEORV32
:desktop_computer: A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
This project hasn't been onboarded to LFX Insights.
OpenXiangShan
Open-source high-performance RISC-V processor
This project hasn't been onboarded to LFX Insights.
Project XLS
XLS: Accelerated HW Synthesis
This project hasn't been onboarded to LFX Insights.
RI5CY
CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
This project hasn't been onboarded to LFX Insights.
SpinalHDL
Scala based HDL
This project hasn't been onboarded to LFX Insights.
Xilinx Runtime
Run Time for AIE and FPGA based platforms
This project hasn't been onboarded to LFX Insights.