18 projects
Yosys Open SYnthesis Suite
Yosys is an open-source framework for RTL synthesis and formal verification of digital circuits. It takes input in HDL formats like Verilog and VHDL, performs synthesis and optimization of digital logic, and can output to various formats for FPGA implementation or ASIC design flows.
1,174
316
$14M
OpenROAD
OpenROAD is an integrated chip physical design tool that performs RTL-to-GDS implementation of digital circuits. It provides automated placement and routing capabilities for electronic design automation (EDA), aiming to produce manufacturable layouts from RTL specifications with minimal human intervention.
856
101
$457M
Chipyard
An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
659
96
$1.6M
CIRCT
CIRCT (Circuit IR Compilers and Tools) is a framework for building circuit design tools and compilers, extending LLVM's infrastructure to support hardware design and synthesis. It provides intermediate representations and compiler tools for describing and manipulating circuits at various levels of abstraction.
542
125
$9M
CHIPS Alliance Projects
The CHIPS Alliance develops high-quality, open source hardware designs relevant to silicon devices and FPGAs.
400
65
$2.1M
Verilog to Routing
Verilog-to-Routing (VTR) is an open-source CAD tool designed for FPGA architecture and CAD research. It provides a complete flow from Verilog HDL to FPGA routing, including synthesis, packing, placement, and routing for FPGA architectures.
218
60
$217M
GDSFactory
GDSFactory is a Python library for creating, manipulating and simulating photonic integrated circuits. It provides tools for automated layout generation of photonic and electronic components using geometric descriptions, with support for parametric cell generation and circuit simulation.
182
47
$6.1M
ARC GNU Toolchain
Repository containing releases of prebuilt GNU toolchains for DesignWare ARC Processors from Synopsys (available from "releases" link below).
CircuitVerse
CircuitVerse Primary Code Base
FireSim
FireSim: Fast and Effortless FPGA-accelerated Hardware Simulation with On-Prem and Cloud Flexibility
GHDL
VHDL 2008/93/87 simulator
KLayout
KLayout Main Sources
KiCad
This is an active mirror of the KiCad development branch, which is hosted at GitLab (updated every time something is pushed). Pull requests on GitHub are not accepted or watched.
Logisim Evolution
Digital logic design tool and simulator
Qucs-S
Qucs-S is a circuit simulation program with Qt-based GUI
RI5CY
CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
Summer of Making
💡 Join 1,000 teenagers and make your first PCB with a $100 grant!